1. Field of the Invention
The present application relates generally to data processing, and more particularly to a computer implemented method and apparatus for testing a ring of non-scan latches with logic built-in self-test.
2. Description of the Related Art
Data processing systems use increasingly complex circuitry, logic, and other electronic components to efficiently process data. Many times, it is financially advantageous to build computer chips that may be tested with on board logic built-in self-test (LBIST). Conventional logic built-in self-test allows chips to be tested and reevaluated when installed, during start-up, or at any other time. Logic built-in self-test helps diagnose fabrication problems more effectively, saving time and money.
However, logic built-in self-test requires the ability to scan or shift data through latch elements of a design in order to load logic built-in self-test patterns and to capture the test results afterwards. The logic built-in self-test test patterns are loaded into the logic to ensure that the logic is functioning properly and to create the expected test data or results. Scannable latches allow data values to be directly loaded to the scannable latch. Non-scan latches are not directly loadable. As a result, a non-scan latch must have a value clocked in. Scannable latches require more area and may be slightly slower than non-scan latches. As a result, it is financially advantageous to use as large a proportion of non-scan latches as possible.
In order to be able to test non-scan latches with logic built-in self-test, the depth of non-scan latches is typically limited to a depth of three or less in a data pipeline. Additionally, no loop-backs from non-scan latches could be tested because such loops prevented loading predictable values in the non-scan latches from predictable scan latches. A loop back refers to an output of a non-scan latch interconnect to an input of another non-scan latch which is located before the non-scan latch with respect to data flow.
Consequently, a series of non-scan latches or multiple non-scan latches configured in a loop or ring is called a ring of non-scan latches. Testing of this type of circuit has been discouraged because the ring of non-scan latches appears as an infinite number of non-scan latches to the logic built-in self-test. The infinite appearance of the ring of non-scan latches violates the depth limit and no loop requirements of logic built-in self-test. Consequently, testing rings of non-scan latches using logic built-in self-test has been impracticable.